module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
	localparam IDLE=3'b000;
	localparam S1=3'b001;
	localparam S2=3'b010;
	localparam S3=3'b011;
	localparam S4=3'b100;
	localparam S5=3'b101;
	localparam S6=3'b110;
	localparam S7=3'b111;
	
	reg [2:0]state;
	reg [2:0]next_state;

	always@(posedge clk)begin
		if(reset)begin
			state<=IDLE;
		end
		else begin
			state<=next_state;
		end
	end
	
	always@(*)begin
		case(state)
			IDLE:begin
				next_state=(x)?S1:IDLE;
				z=1'b0;
			end
			S1:begin
				next_state=(x)?S4:S1;
				z=1'b0;
			end
			S2:begin
				next_state=(x)?S1:S2;
				z=1'b0;
			end
			S3:begin
				next_state=(x)?S2:S1;
				z=1'b1;
			end
			S4:begin
				next_state=(x)?S4:S3;
				z=1'b1;
			end
		endcase
	end
	
endmodule